Design of Displaying 0-15 on 7-segment Display using Logic Gates

In another blog, I explained how to develop the digital design for a BCD to 7-segment decoder on FPGA. But in that case, we only displayed numbers 0-9 using only one 7-segment display. Now we will learn how to develop the digital design to display numbers 0-15 using two 7-segment displays.

Our general circuit block diagram will look like this. Keep in mind that we require a 4-bit input to display up to number 15.

For this circuit, we will need a comparator that outputs 1 if the input value is greater than 9 or 0 otherwise. Also, we will need a substracting circuit to subtract 9 from the input value if it is greater than 9. The output from the comparator will drive the input for our Display 1. Also, the output from the comparator will drive a 2×1 multiplexer which will switch between its two inputs. If the comparator outputs 0 the multiplexer will output the original input value to Display 0. If the comparator outputs 1 the multiplexer will select the output from the subtractor as the output.

Now we can draw the truth tables for our comparator and subtraction circuits.

Comparator Circuit

Now we will develop the logic for the output of the comparator using a Karnaugh map.

Y = In3 * In2 + In3 * In1

Subtractor Circuit

The logic can be developed similarly.

A3 = 0

A2

A2 = In2 * In1

A1

A1 = In2 * ~(In1)

A0

A0 = In1 * In0 + In2 * In0

2×1 Multiplexer

The truth table for the multiplexer is as follows.

The logic can be developed using Karnaugh maps.

F = (~S) * V + S * A

We can improve the circuit further for displaying 0-31 by increasing the number of input bits to 5 and by adding new comparator and subtraction circuits in a similar manner.

Read this blog to see the implementation of this design on Terasic DE10-Lite FPGA.

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